Non-volatile memories comprise an important component in numerous electronic devices in use today. An especially useful type of non-volatile memory is the EEPROM (electrically erasable programmable read-only memory). Flash memory (also referred to as Flash EEPROM memory) is a type of EEPROM memory; a distinctive feature of Flash EEPROMs is the possibility of erasing large groups of memory cells simultaneously). For example, the erase process may be applied to the array globally (full chip erase) or partially by a particular portion of the array (sector erase). The groups of memory cells which are simultaneously erased have their source electrodes connected to a common source line.
The cells of Flash memory typically incorporate a double gate MOSFET transistor. The double gate MOSFET transistor comprises an electrically isolated polysilicon gate (the floating gate) placed above a channel region with the interposition of a gate dielectric (typically an oxide of silicon, referred to as a tunnel oxide). A control gate, typically fabricated using a second polysilicon layer, is insulatively disposed over the floating gate. The double gate MOSFET may be programmed by Fowler-Nordheim tunneling or by channel hot electron injection at the drain region, and is erased by Fowler-Nordheim tunneling. The present invention relates to EEPROM memories where both programming and erase are accomplished by Fowler-Nordheim tunneling.
When the floating gate stores a negative charge, the double gate MOSFET has a relatively high threshold voltage and the associated Flash memory cell is said to be in an erased state. When a Flash memory cell is in an erased state, the negative charge stored on the floating gate prevents the double gate MOSFET from conducting at the voltages applied during a read operation.
When the floating gate stores a neutral or positive charge, the double gate MOSFET has a relatively low threshold voltage and the associated Flash memory cell is said to be in a programmed state. When a Flash cell is in a programmed state, the neutral or positive charge stored on the floating gate enables the double gate MOSFET to conduct at the voltages applied during a read operation.
Variations occur in the size and composition of double gate MOSFETs during their fabrication. As a result, some Flash cells can have slightly thicker or thinner tunnel oxide. The tunnel oxide thickness variation results in changes in the threshold voltage. In general, the threshold voltage of an erased cell is typically a positive value, Vte. The threshold voltage of a programmed cell is typically a negative value, Vtp. The difference between Vte and Vtp is referred to as the program margin, Vpm:Vpm=Vte−Vtp  (1)A relatively large program margin Vpm is desirable because a large program margin Vpm makes it easier to distinguish a programmed cell from an erased cell. In other words, a large value for Vpm makes it easy to read the cell content.
Due to wear-out mechanisms in Flash cells, the program margin Vpm is not stable; rather, Vpm decreases with each program/erase cycle. Over the course of many program/erase cycles, the margin is reduced to the point that the cell fails—the contents can no longer be read reliably. Over-programming and over-erasing a Flash cell causes the diminution of Vpm to occur more rapidly. Thus, in order to maximize the Flash memory cell (and hence, the Flash memory array) operating lifetime, the program and erase operations must be well-controlled. In particular, the program operation must raise the floating gate potential sufficiently to achieve an adequate value for Vtp, but must at the same time provide for limiting the floating potential to avoid over-programming the cell.
In the prior art, methods for control of the cell programming operation have been directed to limiting the potential of the bitline, as in U.S. Pat. No. 6,865,110 to Jae-Kwan Park. U.S. Pat. No. 6,507,067 to Fratin et al. describes a Flash EEPROM comprising single-transistor Flash memory cells. The Flash EEPROM incorporates a current limiting resistor in association with a diode-based clamp to provide a voltage limitation on a common source line during an erase operation. The diode-based clamp lacks a capability for convenient adjustment of the source line potential, relying upon a diode turn-on characteristic to limit the source line potential. The configuration described in the '067 patent does not enable the source line potential to provide a direct measure of the floating gate potential during a programming operation, as described infra for the present invention. What is needed is a means for providing improved control of the potential coupled to the floating gate of a Flash memory device during programming. In particular, an approach that is appropriate to a two-transistor Flash cell configuration is desired, since the two-transistor configuration is commonly employed in a substantial number of Flash memory configurations.